Subject: [PATCH] pci-ids: PCI_VENDOR / DEVICES Targets VMAware check: PCI_VENDOR / DEVICES PCI vendor, device and subsystem IDs that read as Red Hat / QEMU, and the ICH9 southbridge layout OVMF expects to find at 1f:0. Applies to QEMU v11.1.1. Apply from the source root with: patch -p1 < 03-pci-ids.patch --- diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index f2448e9..4eea405 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -57,8 +57,8 @@ extern bool pci_available; #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 /* QEMU/Bochs VGA (0x1234) */ -#define PCI_VENDOR_ID_QEMU 0x1234 -#define PCI_DEVICE_ID_QEMU_VGA 0x1111 +#define PCI_VENDOR_ID_QEMU 0x1002 // "???" | AMD/ATI Vendor ID Replacement from 0x1234 +#define PCI_DEVICE_ID_QEMU_VGA 0x164e // "???" | AMD/ATI Vendor ID Replacement from 0x1111 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 /* VMWare (0x15ad) */ @@ -77,9 +77,9 @@ extern bool pci_available; #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ -#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 -#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 -#define PCI_SUBDEVICE_ID_QEMU 0x1100 +#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 // VirtIO devices | IVSHMEM Driver | Looking Glass +#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x8086 // VirtIO devices | IVSHMEM Driver | Looking Glass +#define PCI_SUBDEVICE_ID_QEMU 0x0000 // VirtIO devices | IVSHMEM Driver | Looking Glass /* legacy virtio-pci devices */ #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 @@ -100,21 +100,21 @@ extern bool pci_available; */ #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 -#define PCI_VENDOR_ID_REDHAT 0x1b36 -#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 -#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 +#define PCI_VENDOR_ID_REDHAT 0x1022 // "Red Hat, Inc." | AMD Vendor ID Replacement from 0x1b36 +#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x57a3 // "QEMU PCI-PCI bridge" | AMD Device ID Replacement from 0x0001 | hw/pci-bridge/pci_bridge_dev.c +#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 // TODO: find device_id | AMD Device ID Replacement from 0x???? | hw/char/serial-pci.c #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 -#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 +#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x1482 // "QEMU PCIe Host bridge" | AMD Device ID Replacement from 0x0008 | hw/pci-host/gpex.c #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b -#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c -#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d -#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e +#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x1483 // "QEMU PCIe Root Port" | AMD Device ID Replacement from 0x000c | hw/pci-bridge/gen_pcie_root_port.c +#define PCI_DEVICE_ID_REDHAT_XHCI 0x149c // "QEMU XHCI Host Controller" | AMD Device ID Replacement from 0x000d | hw/usb/hcd-xhci-pci.c +#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x57ad // "Red Hat, Device ID: 000E" | AMD Device ID Replacement from 0x000e | hw/pci-bridge/pcie_pci_bridge.c #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index 16034aa..5c33c9e 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -178,6 +178,7 @@ #define PCI_VENDOR_ID_AMD 0x1022 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_SCSI 0x2020 +#define PCI_DEVICE_ID_AMD_SATA 0x43f6 // SATA controller [0106] | hw/ide/ich.c #define PCI_VENDOR_ID_HP 0x103c @@ -241,7 +242,7 @@ #define PCI_DEVICE_ID_INTEL_82378 0x0484 #define PCI_DEVICE_ID_INTEL_82441 0x1237 #define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 -#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x14db // PCI bridge [0604] | hw/pci-bridge/i82801b11.c #define PCI_DEVICE_ID_INTEL_82801D 0x24CD #define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab #define PCI_DEVICE_ID_INTEL_NVME 0x5845 diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index 2c35dd0..2b6a39c 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -128,7 +128,7 @@ struct ICH9LPCState { #define ICH9_LPC_DEV 31 #define ICH9_LPC_FUNC 0 -#define ICH9_A2_LPC_REVISION 0x2 +#define ICH9_A2_LPC_REVISION 0x51 // ISA bridge [0601] | hw/isa/lpc_ich9.c #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ #define ICH9_LPC_PMBASE 0x40 @@ -177,7 +177,7 @@ struct ICH9LPCState { #define ICH9_GPIO_GSI "gsi" /* D31:F2 SATA Controller #1 */ -#define ICH9_SATA1_DEV 31 +#define ICH9_SATA1_DEV 20 #define ICH9_SATA1_FUNC 2 /* D31:F0 power management I/O registers @@ -213,7 +213,7 @@ struct ICH9LPCState { /* D31:F3 SMBus controller */ #define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" -#define ICH9_A2_SMB_REVISION 0x02 +#define ICH9_A2_SMB_REVISION 0x71 // SMBus [0c05] | hw/i2c/smbus_ich9.c #define ICH9_SMB_PI 0x00 #define ICH9_SMB_SMBMBAR0 0x10 @@ -230,7 +230,7 @@ struct ICH9LPCState { #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) /* D31:F3 SMBus I/O and memory mapped I/O registers */ -#define ICH9_SMB_DEV 31 +#define ICH9_SMB_DEV 20 #define ICH9_SMB_FUNC 3 #define ICH9_SMB_HST_STS 0x00 diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index edf9783..00365e1 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -864,7 +864,7 @@ static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope) aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG, aml_int(0x60), 0x0C)); /* Fields declarion has to happen *after* operation region */ - field = aml_field("PCI0.SF8.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + field = aml_field("PCI0.LPCB.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); aml_append(field, aml_named_field("PRQA", 8)); aml_append(field, aml_named_field("PRQB", 8)); aml_append(field, aml_named_field("PRQC", 8)); diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index f4556ad..547a901 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -694,7 +694,7 @@ static void mch_class_init(ObjectClass *klass, const void *data) set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->desc = "Host bridge"; dc->vmsd = &vmstate_mch; - k->vendor_id = PCI_VENDOR_ID_INTEL; + k->vendor_id = PCI_VENDOR_ID_AMD; /* * The 'q35' machine type implements an Intel Series 3 chipset, * of which there are several variants. The key difference between diff --git a/hw/core/qdev.c b/hw/core/qdev.c index e2aab3d..9131b5d 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -765,7 +765,7 @@ static void device_class_init(ObjectClass *class, const void *data) * hotpluggable. Devices that shouldn't be hotpluggable, * should override it in their class_init() */ - dc->hotpluggable = true; + dc->hotpluggable = false; dc->user_creatable = true; vc->get_id = device_vmstate_if_get_id; rc->get_state = device_get_reset_state; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f064aa2..cfdbbc1 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1689,7 +1689,7 @@ static void pc_machine_class_init(ObjectClass *oc, const void *data) pcmc->pci_enabled = true; pcmc->has_acpi_build = true; - pcmc->smbios_defaults = true; + pcmc->smbios_defaults = false; pcmc->gigabyte_align = true; pcmc->has_reserved_memory = true; pcmc->enforce_amd_1tb_hole = true;