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d94772ddc249652a07b66a2277925c940deaf9f3
vfio-native/patches/qemu/09-firmware-chain.patch
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Subject: [PATCH] acpi: clear the remaining VMAware FIRMWARE chain links
Targets VMAware check: FIRMWARE
01-firmware cleared the FIRMWARE links known when it was written. Current
VMAware adds more DSDT fingerprints to the same chain, and firmware() returns
on the first match, so the technique keeps firing until every link is gone.
This clears the rest, taking a q35 guest to 0 detections on both the v2.8.1
release and current HEAD. Each change is a rename or a byte-neutral rewrite of
emitted AML; none alters ACPI semantics.
Links cleared:
- PCI interrupt-link query methods IQST/IQCR and the PRR0/PRRI resource
template/field -> PSTA/PCRS/PRS0/PRSI
- TPM Physical Presence Interface regions/method TPP2/TPP3/TPFN -> PPI2/PPI3/PPIF
- zeroed _S5 SLP_TYP: emit the 2-element package form
- ACPI0006 _HID in \_GPE: declared by its full path \_GPE._HID; the
object stays, because macOS will not power off without it
- Q35 MMCONFIG reservation device MCFG -> PCMM
- synthetic GSI link devices: give the no-op _DIS/_SRS a body so the
empty-stub descriptor no longer matches
- PCIe _OSC capability mask: And() operands swapped (commutative)
- PIRQ link _PRS: list the identical IRQ set as {11, 10, 5} so the fixed
5/10/11 descriptor differs
Applies to QEMU v11.1.2, on top of 01-firmware. From the source root:
patch -p1 < 09-firmware-chain.patch
diff --git a/hw/acpi/pci.c b/hw/acpi/pci.c
index 8c7ed1047..0d6a95d67 100644
--- a/hw/acpi/pci.c
+++ b/hw/acpi/pci.c
@@ -326,8 +326,8 @@ Aml *build_pci_host_bridge_osc_method(bool enable_native_pcie_hotplug)
* Allow SHPC (PCI bridges can have SHPC controller)
* Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
*/
- aml_append(if_ctx, aml_and(a_ctrl,
- aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
+ aml_append(if_ctx, aml_and(
+ aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl, a_ctrl));
if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
/* Unknown revision */
diff --git a/hw/acpi/tpm.c b/hw/acpi/tpm.c
index e70377598..d7c234cc5 100644
--- a/hw/acpi/tpm.c
+++ b/hw/acpi/tpm.c
@@ -39,10 +39,10 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)
* the PPI code and parameter (PPRQ, PPRM) to the firmware.
*/
aml_append(dev,
- aml_operation_region("TPP2", AML_SYSTEM_MEMORY,
+ aml_operation_region("PPI2", AML_SYSTEM_MEMORY,
aml_int(ppi_base + 0x100),
0x5A));
- field = aml_field("TPP2", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
+ field = aml_field("PPI2", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
aml_append(field, aml_named_field("PPIN", 8));
aml_append(field, aml_named_field("PPIP", 32));
aml_append(field, aml_named_field("PPRP", 32));
@@ -55,11 +55,11 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)
aml_append(dev,
aml_operation_region(
- "TPP3", AML_SYSTEM_MEMORY,
+ "PPI3", AML_SYSTEM_MEMORY,
aml_int(ppi_base +
0x15a /* movv, docs/specs/tpm.rst */),
0x1));
- field = aml_field("TPP3", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+ field = aml_field("PPI3", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
aml_append(field, aml_named_field("MOVV", 8));
aml_append(dev, field);
@@ -67,7 +67,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)
* DerefOf in Windows is broken with SYSTEM_MEMORY. Use a dynamic
* operation region inside of a method for getting FUNC[op].
*/
- method = aml_method("TPFN", 1, AML_SERIALIZED);
+ method = aml_method("PPIF", 1, AML_SERIALIZED);
{
Aml *op = aml_arg(0);
ifctx = aml_if(aml_lgreater_equal(op, aml_int(0x100)));
@@ -164,7 +164,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)
/* get opcode flags */
aml_append(ifctx2,
- aml_store(aml_call1("TPFN", op), op_flags));
+ aml_store(aml_call1("PPIF", op), op_flags));
/* if func[opcode] & TPM_PPI_FUNC_NOT_IMPLEMENTED */
ifctx3 = aml_if(
@@ -325,7 +325,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)
op));
/* get opcode flags */
- aml_append(ifctx2, aml_store(aml_call1("TPFN", op),
+ aml_append(ifctx2, aml_store(aml_call1("PPIF", op),
op_flags));
/* if func[opcode] & TPM_PPI_FUNC_NOT_IMPLEMENTED */
ifctx3 = aml_if(
@@ -397,7 +397,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)
op));
/* get opcode flags */
- aml_append(ifctx2, aml_store(aml_call1("TPFN", op),
+ aml_append(ifctx2, aml_store(aml_call1("PPIF", op),
op_flags));
/* return confirmation status code */
aml_append(ifctx2,
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4001d9d69..087d5f778 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -515,7 +515,7 @@ static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
Aml *dev;
Aml *crs;
Aml *method;
- uint32_t irqs[] = {5, 10, 11};
+ uint32_t irqs[] = {11, 10, 5};
dev = aml_device("%s", name);
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
@@ -527,7 +527,7 @@ static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
aml_append(dev, aml_name_decl("_PRS", crs));
method = aml_method("_STA", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_return(aml_call1("IQST", reg)));
+ aml_append(method, aml_return(aml_call1("PSTA", reg)));
aml_append(dev, method);
method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
@@ -535,12 +535,12 @@ static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
aml_append(dev, method);
method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_return(aml_call1("IQCR", reg)));
+ aml_append(method, aml_return(aml_call1("PCRS", reg)));
aml_append(dev, method);
method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
- aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
- aml_append(method, aml_store(aml_name("PRRI"), reg));
+ aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRSI"));
+ aml_append(method, aml_store(aml_name("PRSI"), reg));
aml_append(dev, method);
return dev;
@@ -569,9 +569,11 @@ static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
* _DIS can be no-op because the interrupt cannot be disabled.
*/
method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_store(aml_int(0), aml_local(0)));
aml_append(dev, method);
method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+ aml_append(method, aml_store(aml_int(0), aml_local(0)));
aml_append(dev, method);
return dev;
@@ -582,28 +584,28 @@ static Aml *build_iqcr_method(bool is_piix4)
{
Aml *if_ctx;
uint32_t irqs;
- Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
+ Aml *method = aml_method("PCRS", 1, AML_SERIALIZED);
Aml *crs = aml_resource_template();
irqs = 0;
aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
- aml_append(method, aml_name_decl("PRR0", crs));
+ aml_append(method, aml_name_decl("PRS0", crs));
aml_append(method,
- aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
+ aml_create_dword_field(aml_name("PRS0"), aml_int(5), "PRSI"));
if (is_piix4) {
if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
- aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
+ aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRSI")));
aml_append(method, if_ctx);
} else {
aml_append(method,
aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
- aml_name("PRRI")));
+ aml_name("PRSI")));
}
- aml_append(method, aml_return(aml_name("PRR0")));
+ aml_append(method, aml_return(aml_name("PRS0")));
return method;
}
@@ -611,7 +613,7 @@ static Aml *build_iqcr_method(bool is_piix4)
static Aml *build_irq_status_method(void)
{
Aml *if_ctx;
- Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
+ Aml *method = aml_method("PSTA", 1, AML_NOTSERIALIZED);
if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
aml_append(if_ctx, aml_return(aml_int(0x09)));
@@ -801,7 +803,7 @@ static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
Aml *resource_template;
/* DRAM controller */
- dev = aml_device("MCFG");
+ dev = aml_device("PCMM");
aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
resource_template = aml_resource_template();
@@ -986,7 +988,11 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
scope = aml_scope("_GPE");
{
- aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
+ /*
+ * macOS needs the GPE block device to reach S5; naming it by full
+ * path keeps it without the byte pattern VMAware matches.
+ */
+ aml_append(scope, aml_name_decl("\\_GPE._HID", aml_string("ACPI0006")));
if (machine->nvdimms_state->is_enabled) {
method = aml_method("_E04", 0, AML_NOTSERIALIZED);
aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
@@ -1193,11 +1199,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(scope, aml_name_decl("_S4", pkg));
}
- pkg = aml_package(4);
+ pkg = aml_package(2);
aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
- aml_append(pkg, aml_int(0)); /* reserved */
- aml_append(pkg, aml_int(0)); /* reserved */
aml_append(scope, aml_name_decl("_S5", pkg));
aml_append(dsdt, scope);
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